Technical Field
The present invention relates to a package substrate, especially relates to a package substrate having embedded circuit, the circuit runs with a top surface coplanar with a top surface of the dielectric material.
Description of Related Art
FIG. 1 Shows a Prior Art.
FIG. 1 shows that U.S. Pat. No. 9,287,250 disclosed a package substrate for chip. A core substrate 30 is configured in a middle layer. A top solder resist layer 70F is configured on a top side of the package substrate, and a bottom solder resist layer 70S is configured on a bottom side of the package substrate. A first circuit layer 158Fa is embedded in a dielectric material 150Fb. A second circuit layer 58S is embedded in a dielectric material 150Sa. Please pay attention to the thickness of the circuit 158Fa and the dielectric material 150Fb where the circuit 158Fa is embedded. The thickness of the dielectric material 150Fb is far greater than the thickness of the circuit 158Fa. Similarly, a thickness of the dielectric material 150Sa is far greater than the thickness of the circuit 58S.
Following the quick development of package technology in the semiconductor industry, a requirement for package density in the semiconductor chip package technology is higher and higher. The thick dielectric material occupies height space a lot. It would be great helpful to advance the density for package technology in thickness direction if the dielectric material above a top surface of the circuit can be smaller or even eliminated.